At a minimum they've got to design a wider issue. Current high-performance superscalar chips like the XuanTie 910 (what this laptop's SoC are built around) are only triple-issue (3-wide superscalar), which gives a theoretical maximum of 3 ipc per core. (And even by RISC standards, RISC-V has pretty "small" instructions, so 3 ipc isn't much compared to 3 ipc even on ARM. E.g., RISC-V does not have any comparison instructions, so comparisons need to be composed of at least a few more elementary instructions). As you widen the issue, that complicates the pipelining (and detecting pipeline hazards).

There's also some speculation that people are going to have to move to macro-op fusion, instead of implementing the ISA directly. I don't think anyone's actually done that in production yet (the macro-op fusion paper everyone links to was just one research project at a university and I haven't seen it done for real yet). If that happens, that's going to complicate the core design quite a lot.

None of these things are insurmountable. They just take people and time.

I suspect manufacturing is probably a big obstacle, too, but I know quite a bit less about that side of things. I mean a lot of companies are already fabbing RISC-V using modern transistor technologies.