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this post was submitted on 29 Jul 2024
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To stick with the analogy, this is like putting a small CPU inside the bottle, so the main CPU<->RAM bottleneck isn't used as often. That said, any CPU, within RAM silicon or not, is still going to have to shift data around, so there will still be choke points, they'll just be quicker. Theoretically.
Thinking about it, this is kind of the counterpart to CPUs having an on-chip cache of memory.
Edit: counterpoint to counterpart